The present invention relates to a semiconductor memory device and more particularly to a semiconductor memory device and a method for arranging signal lines therein which can realize a high bandwidth by embodying chip architecture being comprised of a multi I/O line.
In designing a semiconductor memory device, one of the most important details is to select an appropriate chip architecture. Parameters indicating performance of the semiconductor memory device, for example, power-consumption, operation speed, chip size, etc. are dependent upon the chip architecture. In other words, an excellent flexibility of the chip architecture greatly contributes to satisfaction of the requirements of such parameters. In practical chip architecture, design, as apparent to one skilled in the art, it is further noted that flexibility of the chip architecture enables its base structure to be maintained without any changes, when changing or adding a peripheral circuit, or increasing the density of the semiconductor memory device. Also, the flexibility of the chip architecture can easily respond to these variations. Now, an object of developing a semiconductor memory device includes achieving a high bandwidth in proportion to the high density of a semiconductor memory device. In other words, a concept of the semiconductor memory device has been changed from one of a simple high density memory device to a new one in which the memory device has the high bandwidth and is synchronized with the speed of a system. For example, in the case of memory device having a capacity of 64M or more, in particular, RAM bus dynamic RAM or synchronous dynamic RAM with a mother version as 256M dynamic RAM, one operational cycle should process data of 256 bits. Therefore, to satisfy the development trend of semiconductor memory devices toward the high bandwidth, the architecture of the memory device to be used with a mother version of 256 bits should have an internal bandwidth of 256 bits (one cycle). Many memory device designers are studying an architecture having a possible high bandwidth. Meanwhile, the higher the density of the memory device is, the larger the size of the chip. As a result, reading and writing data is difficult due to the increment for loading of each line. This difficulty creates an absolute need for a new architecture.
FIG. 1 shows a construction of chip architecture for 256M in a conventional semiconductor memory device. Further, the circuit construction of internal columns based on the chip architecture shown in FIG. 1 is disclosed in, for instance, U.S. Pat. No. 5,247,482, entitled "Semiconductor Memory Device With High Speed Write Operation". When selecting a conventional folded bit line structure in order to constitute a 256M DRAM, 32K word lines and 16K bit lines are necessary. Of course, 512 cells will be able to be connected to one bit line, but it is common that 256 cells are connected to one bit line. Therefore, an array of 2M can be activated by one word line. Here, it is assumed that if a refresh cycle corresponds to 16K, two word lines would be enabled in the length direction of the chip by the activation of a row address strobe signal RAS. Thereby, the whole 256M, arrays of 8M would be activated. If the arrays are activated as depicted in FIG. 1 and two pairs of I/O lines are positioned in a sense amplifier area, the number of bits of data processed in a 2M array is 4, which corresponds to the number of I/O lines. Thus, in whole 256M, 16 bits of data can be possessed. Since this differs greatly from a desired internal bandwidth of 256 bits, a practical achievement of high bandwidth is impossible. Further, the high bandwidth can not be realized with the above-mentioned chip architecture. Also, in this chip architecture, loading of I/O lines as well as junction loading of gate transistors for connecting the I/O line to a bit line are great, which can lead to difficulties in developing a voltage on the I/O line upon performance of a read operation. Further, upon performance of a write operation, since the data I/O line shown in FIG. 1 is directly connected to the bit line through the gate transistor, the junction loading and bit line are hurt. For that reason, it is appreciated that the construction of FIG. 1 is not suitable for the high density memory device.
FIG. 2 shows another embodiment of a conventional semiconductor memory device, through which a high bandwidth can be achieved, compared with that of FIG. 1 and in which the line loading of FIG. 1 is greatly reduced. FIG. 2 is disclosed in "Circuit Techniques For a Wide Word I/O Path 64 Mega DRAM" on pp. 133-134 of a paper in "1991 SYMPOSIUM ON VLSI CIRCUITS". For details of FIG. 2, the above paper will be helpful. In the figure, the loading of I/O lines is reduced by using sub I/O lines and a local I/O lines. Also, a predetermined number of sense amplifiers are integrated to the sub I/O line, to transmit data to the local I/O line through a differential amplifier. This prior art may have an internal bandwidth to some extent, but it is disadvantageous in that the number of NMOS transistors through which data is transmitted is large, upon performance of a write operation. FIG. 3 is a block diagram illustrating the data I/O lines of FIG. 2. Upon performance of a write operation, data on the local I/O line is transmitted to a transistor 2 of FIG. 2 by the enable of a signal SEC SELECT having column information of a selected block, but if a signal YWRITE for determining sub I/O line is enabled, the data is transmitted to the sub I/O line through a transistor 4. If an information signal S/A SELECT of a predetermined bit line selected in a plurality of bit lines connected to a single sub I/O line is enabled, the data is transmitted to the bit line through a transistor 10. As mentioned above, when the write operation is performed, since the data transmission is made from the I/O line to the bit line only through three NMOS transistors, it is seriously disadvantageous in performing a write operation in a high integrated memory device having great line loading.